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Aleksey Baranov
2026-03-17 18:33:09 +03:00
parent 5cfa6ca8eb
commit b02a14aa4a
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4T4R TDD/FDD 4T4R B3 General.md → 4T4R FDD/FDD 4T4R B3 General.md
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ATE 4T4R FDD/Files/vswr_image.png → 4T4R FDD/Files/vswr_image.png
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ATE 4T4R FDD/VSWR.md → 4T4R FDD/VSWR.md
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@@ -9,7 +9,7 @@ Voltage Standing Wave Ratio (КСВН - коэффициент стоячей в
### Архитектура
Архитектура **SWR** TDD модуля
![[ATE 4T4R FDD/Files/vswr_image.png]]
![[4T4R FDD/Files/vswr_image.png]]
1. Архитектура модуля
1. Одна плата на 4 канала
1. Интерфейсный коннектор
ATE 4T4R FDD/FDD 4T4R B3 General.md → 4T4R TDD/TDD 4T4R General.md
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#ATE #4t4r #b3
#ATE #4t4r #tdd #b40 #n78 #n79 #b38
### Action (основные тезисы)
1. Начало тестирования - на оборудовании b3. Возможен на второй комплект.
2. Начало разработки - конец марта