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Alexey Baranov
2026-03-10 10:27:06 +03:00
parent d60f8ac36c
commit ac71e3dca2
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ATE 4T4R FDD/FDD 4T4R B3 General.md
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2. Архитектура модуля
1. Одна плата на 4 канала
2. Интерфейсный коннектор
1. 20 pin connector
2. I2C
3. 3V3
4. 5V
1. 20 pin connector (FX27-40S-0.8SV)
1. ![[Pasted image 20260310102456.png]]
2. 3V8 - VSWRM
3. I2C_3V3
1. ADC (ADS1119IRTET) 0x40
2. MAX7315ATE+ 0x20
3. EEPROM CAT24C256WI-GT3 0x50
4. GPIO
1. FWD_SW_CTRL1_3V3
2. FWD_SW_CTRL2_3V3
3. REFL_SW_CTRL1_3V3
4. FWD_SW_CTRL2_3V3
3. Необходимость наличия крышки над платой.
3. Тестирование и оснастка:
1. Выполняется в сборе с RU вместе с фильтром. **ОК**