diff --git a/ATE B8B20/B8B20 Arhitecture.md b/ATE B8B20/B8B20 Arhitecture.md
index 9d47e87..5ead4e8 100644
--- a/ATE B8B20/B8B20 Arhitecture.md	
+++ b/ATE B8B20/B8B20 Arhitecture.md	
@@ -45,8 +45,9 @@ https://c.yadro.com/pages/viewpage.action?pageId=1096644403
 HLBD Signal Path
 ![[pamb8b20_HLBD_signal.png]]
 1. Архитектура:
-	1. 2 канала TX на плате и 1 DPD
-	2. Power Supply:
+	1. 2 канала TX 
+	2. 1 DPD
+	3. Power Supply:
 		1. 12V0_VDD 
 			1. Current = 0.12A 
 				1. Converted to:
@@ -56,17 +57,36 @@ HLBD Signal Path
 			1. Current = 6.5A
 		3. 48V0_PA_CH2 
 			1. Current = 6.5A
-2. Интерфейсы PAM:
+			   
+2. Connection PAM:
 	1. 40 PIN Connection to DM
 		1. 66H8-M040S1075R01
 			1. I2C - Bus 
 			2. GPIO
-				1. ALARM_VDD_AMPS_TX (INT_A)
-				2. ALARM_REFL_PROT (INT_B)
-				3. EXP_RST_3V3
-				4. EN_TX_CH1_3V3
-				5. EN_TX_CH2_3V3
-3. Digital Periferal of I2C Bus:
+				1. FLAG Refl / Vdd Error:
+					1. ALARM_VDD_AMPS_TX (INT_A)
+					2. ALARM_REFL_PROT (INT_B)
+				2. Reset Expander:
+					1. EXP_RST_3V3   
+				3. Bais ON 
+					1. EN_TX_CH1_3V3
+					2. EN_TX_CH2_3V3
+			3. PS:
+				1. 48V0_PA_CH1_VDD
+				2. 48V0_PA_CH2_VDD
+				3. 12V0_VDD
+				4. 3V3_TX_ISO
+				5. 3V3_TX_DVCC
+3. RF SIgnal Path:
+	1. INPUT:
+		1. RF_TX_CH1
+		2. RF_TX_CH2
+	2. OUTPUT:
+		1. RF_TX1_OUT
+		2. RF_TX2_OUT
+		3. RF_DPD_OUT
+		   
+4. Digital Periferal of I2C Bus:
 	1. **Bias Controller**
 		1. BGMC1210E6327XUMA
 		2. Adr: 0x40
@@ -110,7 +130,7 @@ HLBD Signal Path
 		5. GPIO to DM
 			1. EXP_RST_3V3
 
-4. Интерфейсы:
+5. Интерфейсы:
 	1.