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vault backup: 2026-03-19 11:52:12

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Aleksey Baranov
2026-03-19 11:52:12 +03:00
parent 6eac022490
commit 5661be3f66
1 changed files with 5 additions and 2 deletions
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4T4R FDD/DM - DMBPRD470101A.md
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@@ -16,9 +16,10 @@ General HLBD
Clock Distribution Clock Distribution
![[4T4R FDD/Untitled Diagram.svg]] ![[4T4R FDD/Untitled Diagram.svg]]
![[Clock Distribution.svg]] ![[Clock Distribution.svg]]
1. Архитектура модуля: 1. Архитектура RU модуля:
1. Расположение интерфейсов TOP и BОTTOM ? 1. Расположение интерфейсов TOP и BОTTOM ?
2. DM 2. DM
1.
3. PA 3. PA
4. SWR 4. SWR
5. 5.
@@ -41,7 +42,9 @@ Clock Distribution
1. 40 pin connector (FX27-40S-0.8SV) 1. 40 pin connector (FX27-40S-0.8SV)
2. Power: 3V8 2. Power: 3V8
3. I2C 3. I2C
3. Необходимость наличия крышки над платой. 3. OPT (eCPRI) - 2 коннектора
4. AISG 2.0
5. Необходимость наличия крышки над платой.
--- ---
### ATE Production Flow ### ATE Production Flow